Burn-in is a well-known technique to promote improved reliability of semiconductor chips. It is essentially a procedure to eliminate latent manufacturing flaws in an element or assembly, which, if left undetected, would result in early field failures. Burn-in is accomplished by the application, on an accelerated basis, of environmental and operational stresses to the device or assembly under test. The stress factors include both temperature and design limit voltages.
Burn-in is performed at many levels of the component hierarchy of systems which contain semiconductors, e.g., computers. For instance, it is performed on the unpackaged chip, the second level assembly, packaged components, and higher levels through the final system level burn-in. It is often most cost-effective to conduct burn-in at the lowest packaging level. There, the stresses can be optimized to the specific level of the package, such that higher levels of packaging are not exposed to more stressful conditions than they would otherwise be designed to accomodate. This level of testing also prevents flawed devices from being carried through subsequent manufacturing steps, thereby causing increased costs which result from possible re-work or, potentially, the discarding of higher level assemblies.
Classically, burn-in of first level packages has been accomplished by mounting the chips in individual sockets of a burn-in circuit board. The entire circuit board is then subjected to the stress environment. This technique requires considerable handling of chip packages and is quite expensive. Recently, a new packaging method known as "Tape-Automated Bonding" or TAB packaging has come into vogue. In this method, chips are bonded to a carrier tape, and the tape (with mounted chips) is stored on a reel for use in subsequent automated operations.
The TAB carrier tape is similar to a 35 mm film and is a multi-layer structure with an insulating film base and a conductive layer, typically gold-plated copper. Circuit patterns are formed on the tape to define both chip mounting locations and leads which will make contact with the chip and then fan out. At each location, an integrated circuit chip is positioned adjacent to mounting location pads so that the chip contact pads are aligned with the leads, and then all pads are thermally bonded to the leads.
While the TAB process provides a convenient way of handling chips in automated assembly operations, TAB burn-in procedures have not seen similar advances as the packaging concept. For instance, in U.S. Pat. No. 4,779,047 to Solstad, et al, a plurality of integrated circuits mounted on a short strip of carrier tape are inserted into a fixture which than makes contact between the circuit's leads and a contact array in the fixture. The fixture and IC strip are than subjected to the burn-in operation. In U.S. Pat. No. 4,716,124 to Yerman et al a TAB tape, including mounted chips, is incremented past a test site where control leads fashioned from portions of the tape carrier are contacted by electrical contacts to enable the testing of each individual chip. In U.S. Pat. No. 4,763,409 to Takekawa, et al, a TAB packaged chip is emplaced in a single-chip test fixture where contacts are made and power applied.
As is clear from the aforementioned references, all continue to perform burn-in tests of TAB-mounted semiconductor devices, either on a one-by-one basis or in small groups.
Another aspect of burn-in testing which has seen some application, is the use of temperature controlled heat exchange baths for application of elevated temperatures to the devices under test. Such systems are shown in U.S. Pat. Nos. 3,560,849 to Ryan, et al; 3,761,808 to Ryan; and 4,745,354 to Fraser. Each of those patents immerses individual semi-conductor devices or groups thereof into a heat exchange bath for the purpose of applying an elevated test temperature. None of the aforementioned references indicate that such a procedure is applicable to TAB packages.
Accordingly, it is an object of this invention to provide a burn-in test apparatus which enables a large number of TAB packaged chips to be simultaneously subjected to burn-in.
It is still another object of this invention to provide a system for subjecting a complete roll of TAB packaged chips to a simultaneous burn-in procedure, while also minimizing the number of interconnections to the TAB roll.
It is further object of this invention to employ a fluid immersion heat stress system with TAB package burn-in apparatus.